module ex(
	input 			clk,
	input			rst,
	input	[31:0]  ex_JumpAddr,
	input 	[31:0] 	ex_BranchAddr,
	input	[31:0] 	ex_Addr,
	input	[7:0]	ex_Code,
	input	[31:0]	ex_RFRead1,
	input	[31:0]	ex_RFRead2,
	input 	[31:0] 	ex_WrData,
	input	[7:0] 	ex_CtrlCode,
	input	[31:0] 	ex_RFWAddr,

	output 	[31:0] 	mem_JumpAddr,
	output	[31:0] 	mem_Addr,
	output	[7:0]	mem_Code,
	output	[31:0]	mem_ALURes,
	output	[31:0] 	mem_WrData,
	output	[31:0]	mem_RFWAddr
);


reg	[31:0]  reg_JumpAddr;
reg [31:0] 	reg_BranchAddr;
reg	[31:0] 	reg_Addr;
reg	[7:0]	reg_Code;
reg	[31:0]	reg_RFRead1;
reg	[31:0]	reg_RFRead2;
reg [31:0] 	reg_WrData;
reg	[7:0] 	reg_CtrlCode;
reg	[31:0] 	reg_RFWAddr;

assign mem_Addr = reg_Addr;
assign mem_Code = reg_Code;
assign mem_WrData = reg_WrData;
assign mem_RFWAddr = reg_RFWAddr;
// assign mem_CtrlCode = reg_CtrlCode;

always @(posedge clk or negedge rst) begin
	if (!rst) begin
		// reset
		reg_Addr <= 0;
		
	end
	else begin
		reg_JumpAddr <= ex_JumpAddr;
		reg_BranchAddr <= ex_BranchAddr;
		reg_Addr <= ex_Addr;
		reg_Code <= ex_Code;
		reg_RFRead1 <= ex_RFRead1;
		reg_RFRead2 <= ex_RFRead2;
		reg_WrData <= ex_WrData;
		reg_CtrlCode <= ex_CtrlCode;
		reg_RFWAddr <= ex_RFWAddr;
	end
end
wire pcsinal;
ALU inst_ALU (
	.input_data1    (reg_RFRead1),
	.input_data2    (reg_RFRead2),
	.output_data    (mem_ALURes),
	.ctrl_sinal     (reg_CtrlCode),
	.output_pcsinal (pcsinal)
);

wire sinal;
MUX inst_MUX (
	.sinal    (sinal),
	.in_data0 (reg_JumpAddr),
	.in_data1 (reg_BranchAddr),
	.out_data (mem_JumpAddr)
);

assign sinal = reg_Code[4] & pcsinal;

endmodule